1. Field of the Invention
The present invention relates in general to an apparatus for compressing video data to transmit moving picture data in real time through a transmission medium with a limited band width, and more particularly to an improved motion vector extractor which is capable of rapidly extracting motion vectors from the moving picture data to be transmitted and simplifying its circuit construction.
2. Description of the Prior Art
Recently, digital video transmission systems have utilized a data compression method to transmit moving picture data in real time through a transmission channel with a limited band width to digital video reception systems such as a digital video phone, a digital video conversation system, a digital television and a high definition television. The data compression method is adapted to compress the moving picture data by removing time and spatial redundancies of the moving picture data. The time redundancy removing methods include motion vector estimation and compensation methods for transmitting only motion vectors regarding a moving object or a part of the moving object to have the actual video data transmission effect. This results from the moving picture data having a series of frames corresponding to the moving object. The motion vector estimation method is generally classified into a recursive method and a matching method. In the matching method, there is widely used a block matching algorithm for matching the moving picture data in the unit of block to estimate the motion vectors from the moving picture data.
The ISO/IEC JTC1/SC29/WG11 recommendation proposed by the moving picture expert group (MPEG) specifies a block matching algorithm which finds the motion vectors in the unit of macro block including 16.times.16 pixels. This recommendation also suggests that the motion vectors be estimated in the unit of 1/2 pixel to enhance the accuracy thereof.
On the basis of the above recommendation, the digital video transmission systems comprise a motion vector extractor for extracting a motion vector in a pixel unit smaller than an integer, such as 1/4 pixel or 1/2 pixel, to secure the accuracy of the video data to be transmitted. Such a conventional motion vector extractor produces interpolation pixel data using desired integer pixel data and integer pixel data adjacent up, down, to the left and to the right of the desired integer pixel data. The conventional motion vector extractor calculates a mean absolute difference (referred to hereinafter as "MAD") between the desired integer pixel data and each of the produced interpolation pixel data. Then, the conventional motion vector extractor compares the calculated MADs with one another and calculates the motion vector in accordance with the compared result. In the case of estimating the motion vector in the unit of 1/4 pixel, the conventional motion vector extractor must calculate 16 of 49 interpolation pixel data, adjacent to one side of the desired integer pixel data, and the corresponding MADs. In the case of estimating the motion vector in the unit of 1/2 pixel, the conventional motion vector extractor must calculate 4 of 9 interpolation pixel data, adjacent to one side of the desired integer pixel data, and the corresponding MADs.
However, the above-mentioned conventional motion vector extractor has a disadvantage in that it sequentially calculates one by one the interpolation pixel data related to the desired integer pixel data, resulting in much time being required in calculating the motion vector. Further, the above-mentioned conventional motion vector extractor has another disadvantage in that it must have a complex circuit construction to enhance the motion vector calculating time. The problem with the above-mentioned conventional motion vector extractor will hereinafter be described in detail with reference to FIGS. 1 to 5.
Referring to FIG. 1, there is shown a block diagram of the conventional motion vector extractor for extracting the motion vector in the unit of 1/4 pixel. As shown in this drawing, the conventional motion vector extractor comprises a first interpolation circuit 10 for inputting pixel data b(i,j) of the previous frame (referred to hereinafter as "present pixel data") and pixel data b(i+1,j) of the subsequent block line of the pixel data b(i,j) (referred to hereinafter as "subsequent line pixel data") from first and second input lines 11 and 13, respectively. Here, "i" and "j" designate vertical and horizontal coordinates of the pixel data, respectively. The first interpolation circuit 10 obtains four vertical interpolation pixel data b.sub.0.sup.0 (i,j), b.sub.0.sup.1 (i,j), b.sub.0.sup.2 (i,j) and b.sub.0.sup.3 (i,j) with respect to the pixel data b(i,j) of the previous frame using the pixel data b(i,j) of the previous frame and the subsequent line pixel data b(i+1,j). Then, the first interpolation circuit 10 sequentially supplies the obtained vertical interpolation pixel data b.sub.0.sup.0 (i,j), b.sub.0.sup.1 (i,j), b.sub.0.sup.2 (i,j) and b.sub.0.sup.3 (i,j) to a first register 12. The first register 12 sequentially supplies the vertical interpolation pixel data b.sub.0.sup.0 (i,j), b.sub.0.sup.1 (i,j), b.sub.0.sup.2 (i,j) and b.sub.0.sup.3 (i,j) from the first interpolation circuit 10 to a second interpolation circuit 22 and a second register 14. The second to fifth registers 14, 16, 18 and 20 are connected in series to the first register 12 to delay the vertical interpolation pixel data b.sub.0.sup.0 (i,j), b.sub.0.sup.1 (i,j), b.sub.0.sup.2 (i,j) and b.sub.0.sup.3 (i,j) from the first register 12 by a one pixel interval, respectively. As a result, the fifth register 20 sequentially supplies the vertical interpolation pixel data b.sub.0.sup.0 (i,j), b.sub.0.sup.1 (i,j), b.sub.0.sup.2 (i,j) and b.sub.0.sup.3 (i,j) regarding the present pixel data to the second interpolation circuit 22, whereas the first register 12 sequentially supplies vertical interpolation pixel data b.sub.0.sup.0 (i,j+1), b.sub.0.sup.1 (i,j+1), b.sub.0.sup.2 (i,j+1) and b.sub.0.sup.3 (i,j+1) regarding the subsequent pixel data to the second interpolation circuit 22. The second interpolation circuit 22 combines the vertical interpolation pixel data b.sub.0.sup.0 (i,j), b.sub.0.sup.1 (i,j), b.sub.0.sup.2 (i,j) and b.sub.0.sup.3 (i,j) regarding the present pixel data, supplied from the fifth register 20, and the vertical interpolation pixel data b.sub.0.sup.0 (i,j+1), b.sub.0.sup.1 (i,j+1), b.sub.0.sup.2 (i,j+1) and b.sub.0.sup.3 (i,j+1) regarding the subsequent pixel data, supplied from the first register 12. As a result of the combination, the second interpolation circuit 22 obtains four horizontal interpolation pixel data b.sub.0.sup.k (i,j), b.sub.1.sup.k (i,j), b.sub.2.sup.k (i,j) and b.sub.3.sup.k (i,j) with respect to each of the vertical interpolation pixel data b.sub.0.sup.0 (i,j), b.sub.0.sup.1 (i,j), b.sub.0.sup.2 (i,j) and b.sub.0.sup.3 (i,j).
The conventional motion vector extractor further comprises first to fourth MAD detectors 24, 26, 28 and 30 for inputting pixel data a (i,j) of the present frame from a third input line 15. The first MAD detector 24 sequentially obtains four MADs in the vertical direction on the basis of the pixel data a (i,j) of the present frame from the third input line 15 and the horizontal interpolation pixel data b.sub.0.sup.k (i,j) from the second interpolation circuit 22. Then, the first MAD detector 24 sequentially supplies the obtained four MADs to a comparator 32. Similarly, each of the second to fourth MAD detectors 26, 28 and 30 obtains four MADs in the vertical direction on the basis of the pixel data a (i,j) of the present frame from the third input line 15 and a corresponding one of the horizontal interpolation pixel data b.sub.1.sup.k (i,j), b.sub.2.sup.k (i,j) and b.sub.3.sup.k (i,j) from the second interpolation circuit 22 and then supplies the obtained four MADs to the comparator 32. The comparator 32 compares the MADs from the first to fourth MAD detectors 24, 26, 28 and 30 with one another and detects the motion vector in accordance with the compared result. The second interpolation circuit 22, the first to fourth MAD detectors 24, 26, 28 and 30 and the comparator 32 are operated four times to extract the motion vector regarding one pixel at output line 17.
The first and second interpolation circuits 10 and 22 are operated four times to produce 16 interpolation pixel data on the basis of the following equation (1): EQU b.sub.1.sup.k (i,j)=(4-l)/4{(4-k)b(i,j)/4+kb(i+1,j)/4}+l/4{(4-k)b(i,j+1)/4+kb(i+1,j+1)/4 }(1)
Referring to FIG. 2, there is shown a detailed block diagram of the first interpolation circuit 10 in FIG. 1. As shown in this drawing, the first interpolation circuit 10 includes a first attenuator 34 for inputting the pixel data b(i,j) of the previous frame from the first input line 11, and a second attenuator 36 for inputting the subsequent line pixel data b(i+1,j) from the second input line 13. The second attenuator 36 attenuates the subsequent line pixel data b(i+1,j) from the second input line 13 in such a manner that it can have a 1/4 amplitude. Then, the second attenuator 36 supplies the attenuated subsequent line pixel data b(i+1,j)/4 to a first adder 38. The first adder 38 adds pixel data from a first subtracter 44 to the attenuated subsequent line pixel data b(i+1,j)/4 from the second attenuator 36. As a result of the addition, the first adder 38 obtains the vertical interpolation pixel data b.sub.0.sup.k (i,j). The first adder 38 then supplies the obtained vertical interpolation pixel data b.sub.0.sup.k (i,j) to a multiplexer 40. The multiplexer 40 selectively transfers the vertical interpolation pixel data b.sub.0.sup.k (i,j) from the first adder 38 and the pixel data b(i,j) of the previous frame from the first input line 11 through an output line 35 to the first register 12 in FIG. 1. Namely, at the initial state, the multiplexer 40 transfers the pixel data b(i,j) of the previous frame from the first input line 11 as the vertical interpolation pixel data b.sub.0.sup.k (i,j) through the output line 35 to the first register 12. At the normal state, the multiplexer 40 transfers the vertical interpolation pixel data b.sub.0.sup.k (i,j) from the first adder 38 through the output line 35 to the first register 12.
The first interpolation circuit 10 further includes a sixth register 42 for inputting the vertical interpolation pixel data b.sub.O.sup.k (i,j) selected by the multiplexer 40 through the output line 35. The sixth register 42 delays the vertical interpolation pixel data b.sub.O.sup.k (i,j) from the multiplexer 40 for a predetermined time period and supplies the delayed vertical interpolation pixel data b.sub.O.sup.k (i,j) to the first subtracter 44. The first attenuator 34 attenuates the pixel data b(i,j) of the previous frame from the first input line 11 in such a manner that it can have a 1/4 amplitude. Then, the first attenuator 34 supplies the attenuated pixel data b(i,j)/4 of the previous frame to the first subtracter 44. The first subtracter 44 subtracts the attenuated pixel data b(i,j)/4 of the previous frame from the first attenuator 34 from the delayed vertical interpolation pixel data b.sub.O.sup.k (i,j) from the sixth register 42 and supplies the resultant pixel data to the first adder 38.
In result, the first interpolation circuit 10 produces the four vertical interpolation pixel data on the basis of the following equation (2): EQU b.sub.O.sup.k (i,j)=b.sub.O.sup.k-1 (i,j)-b.sub.O (i,j)/4+b.sub.O (i,j+1)/4(2)
Referring to FIG. 3, there is shown a detailed block diagram of the second interpolation circuit 22 in FIG. 1. As shown in this drawing, the second interpolation circuit 22 includes a third attenuator 46 for inputting the vertical interpolation pixel data b.sub.O.sup.k (i,j+1) of the subsequent pixel data from the first register 12 in FIG. 1 through a first input line 47, and a fourth attenuator 48 for inputting the vertical interpolation pixel data b.sub.O.sup.k (i,j) of the present pixel data from the fifth register 20 in FIG. 1 through a second input line 49. The third attenuator 46 attenuates the vertical interpolation pixel data b.sub.O.sup.k (i,j+1) of the subsequent pixel data from the first register 12 in such a manner that it can have a 1/2 amplitude. Then, the third attenuator 46 supplies the attenuated vertical interpolation pixel data b.sub.O.sup.k (i,j+1)/2 of the subsequent pixel data to second and fourth adders 50 and 56. The fourth attenuator 48 attenuates the vertical interpolation pixel data b.sub.O.sup.k (i,j) of the present pixel data from the fifth register 20 in such a manner that it can have a 1/2 amplitude. Then, the fourth attenuator 48 supplies the attenuated vertical interpolation pixel data b.sub.O.sup.k (i,j)/2 of the present pixel data to the second adder 50 and a third adder 54. The second adder 50 adds the attenuated vertical interpolation pixel data b.sub.O.sup.k (i,j+1)/2 and b.sub.O.sup.k (i,j)/2 from the third and fourth attenuators 46 and 48. As a result of the addition, the second adder 50 produces the horizontal interpolation pixel data b.sub.2.sup.k (i,j).
The second interpolation circuit 22 further includes a fifth attenuator 52 for attenuating the horizontal interpolation pixel data {[b.sub.O.sup.k (i,j+1)+b.sub.O.sup.k (i,j)]/2=b.sub.2.sup.k (i,j)} from the second adder 50 in such a manner that it can have a 1/2 amplitude. The fifth attenuator 52 supplies the attenuated horizontal interpolation pixel data [b.sub.O.sup.k (i,j+1)+b.sub.O.sup.k (i,j)]/4 to the third and fourth adders 54 and 56. The third adder 54 adds the attenuated vertical interpolation pixel data b.sub.O.sup.k (i,j)/2 from the fourth attenuator 48 and the attenuated horizontal interpolation pixel data [b.sub.O.sup.k (i,j+1) +b.sub.O.sup.k (i,j)]/4 from the fifth attenuator 52. As a result of the addition, the third adder 54 produces the horizontal interpolation pixel data b.sub.1.sup.k (i,j). The fourth adder 56 adds the attenuated vertical interpolation pixel data b.sub.O.sup.k (i,j+1)/2 from the third attenuator 46 and the attenuated horizontal interpolation pixel data [b.sub.O.sup.k (i,j+1)+b.sub.O.sup.k (i,j)]/4 from the fifth attenuator 52. As a result of the addition, the fourth adder 56 produces the horizontal interpolation pixel data {b.sub.3.sup.k (i,j)=[3b.sub.O.sup.k (i,j+1)+b.sub.O.sup.k (i,j)]/4.
The second interpolation circuit 22 further includes first to third output lines 51, 53 and 55 connected respectively to the third, second and fourth adders 54, 50 and 56. The second input line 49 transfers the vertical interpolation pixel data b.sub.O.sup.k (i,j) of the present pixel data from the fifth register 20 as the horizontal interpolation pixel data to the first MAD detector 24 in FIG. 1. The first to third output lines 51, 53 and 55 transfer the horizontal interpolation pixel data b.sub.1.sup.k (i,j), b.sub.2.sup.k (i,j) and b.sub.3.sup.k (i,j) from the third, second and fourth adders 54, 50 and 56 to the second to fourth MAD detectors 26, 28 and 30 in FIG. 1, respectively.
Referring to FIG. 4, there is shown a detailed block diagram of each of the first to fourth MAD detectors 24, 26, 28 and 30 in FIG. 1. As shown in this drawing, the MAD detector includes a second subtracter 58 for inputting the pixel data a(i,j) of the present frame and the horizontal interpolation pixel data b.sub.1.sup.k (i,j) regarding the present pixel data through first and second input lines 15 and 59, respectively. The second subtracter 58 subtracts the horizontal interpolation pixel data b.sub.1.sup.k (i,j) regarding the present pixel data from the pixel data a(i,j) of the present frame. As a result of the subtraction, the second subtracter 58 detects a difference between the pixel data a(i,j) of the present frame and the horizontal interpolation pixel data b.sub.1.sup.k (i,j) regarding the present pixel data. Then, the second subtracter 58 supplies the detected difference to a seventh register 60. The first input line 15 is the same as the third input line 15 in FIG. 1. The second input line 59 is connected to the second input line 49, the first output line 51, the second output line 53 or the third output line 55 of the second interpolation circuit 22 in FIG. 1 to input the corresponding horizontal interpolation pixel data b.sub.O.sup.k (i,j), b.sub.1.sup.k (i,j), b.sub.2.sup.k (i,j) or b.sub.3.sup.k (i,j) therefrom. The seventh register 60 temporarily stores the inter-pixel difference from the second subtracter 58 and supplies the temporarily stored inter-pixel difference to an absolute value calculator 62. In result, the seventh register 60 acts to safely transfer the inter-pixel difference from the second subtracter 58 to the absolute value calculator 62. The absolute value calculator 62 obtains an absolute value of the inter-pixel difference from the seventh register 60 and supplies the obtained absolute value to an eighth register 64.
The MAD detector further includes an accumulator 66 for inputting the absolute value of the inter-pixel difference from the eighth register 64. The accumulator 66 adds the absolute value of the inter-pixel difference from the eighth register 64 to an MAD from an output line 61 and transfers the resultant MAD to a ninth register 68. The ninth register 68 transfers the MAD from the accumulator 66 to the output line 61 through tenth to twelfth registers 70, 72 and 74. The ninth to twelfth registers 68, 70, 72 and 74 are connected between the accumulator 66 and the output line 61 to store the four MADs produced between the four vertical interpolation pixel data and the pixel data of the present frame, respectively.
FIG. 5 is a table illustrating the interpolation pixel data from the first and second interpolation circuits 10 and 22 and the MADs from the first to fourth MAD detectors 24, 26, 28 and 30 with respect to the pixel data from the second input line 13 in FIG. 1.
As mentioned above, the conventional motion vector extractor must perform the same operation four times to extract the motion vector with respect to one pixel, resulting in a significant reduction in the motion vector calculating speed. In order to enhance the motion vector calculating speed, the conventional motion vector extractor may perform the interpolation pixel data and MAD detections in a parallel manner. In this case, the circuit becomes very complex in construction.